Domain-Specific RISC-V Processor without Disadvantages

Zdenek Prikryl, codasip, CZ

Abstract

On-chip processors have been traditionally grouped into silos like MCU, DSP, GPU and application processor. Designers have relied on Moore’s law rather than special architectural changes to achieve performance improvements. With gains from Moore’s law becoming more difficult to achieve architectural alternatives are being explored. In many cases what is ideal for an application may be some combination of the traditional categories as a domain-specific processor. Creating a custom instruction set and microarchitecture has traditionally been expensive and often it has been challenging to port enough middleware and software. With the open and free RISC-V ISA, there is a great opportunity to develop a domain-specific processor without the disadvantages of a fully custom ISA. RISC-V allows not only optional standard extensions but allows custom instructions which have been proven to give performance and code density gains for cryptography, DSP and AI algorithms. By creating RISC-V cores using a processor description language, Codasip provides a straightforward way of adding custom instructions and then automatically generating the hardware and software design kits. This paper explains the benefits of custom instructions and the methodology used.

Biography

Dr. Prikryl, CTO at Codasip, has undertaken research at Brno University of Technology which led to the creation of processor development tools at Codasip. Specifically, he was a developer of the methodology to automatically generate hardware and software development kits from a processor description language. Dr. Prikryl has been a chief architect of Codasip Studio for over ten years and has been a chief architect of diverse processor cores including but not limited to 16/32-bit architectures for IoT, 32/64bit DSP oriented architectures or Linux capable architectures. All of these architectures were developed using Studio and many of them were based on RISC-V ISA.