2nd RVF (RISC-V Firmware) - Workshop 2024 - Program

At this web page you find the programme of the 2nd RVF (RISC-V Firmware) - Workshop 2024. You may expand the programme for each session by clicking on the session title. You will find the detailed timetable, presentation titles and author names. If additional information like an abstract, curriculum vitae or (for attendees of the 2nd RVF (RISC-V Firmware) - Workshop 2024 only) slides is available, a link below the presentation title is displayed.

Thursday, October 24, 2024

10:00 - 10:10
Welcome

10:10 - 12:55
Session: Rust Middleware and Libraries
Moderator: Timo Hämäläinen (Tampere University, FI)

10:10	Invited Presentation: Rust for Linux: Linux device driver development in Rust (SoC HUB project) Elias Meyer (Wapice, FI) Slides (Access for event attendees only)
11:10	Break: Coffee/Tea Break
11:40	Hard real-time support for RISC-V in Rust (SoC HUB and TRISTAN projects and RUST community) Henri Lunnikivi (Tampere University, FI) Abstract: We present a case study of implementing RISC-V architectural support for a deeply embedded hard real-time framework: RTIC. In the talk, we focus on how procedural macros are used to generate an abstraction layer between the user-facing framework DSL, and target specific interrupt-management code. Slides (Access for event attendees only)
12:25	From Model to Rust: A modification on an existing MDA-Code-Generation Approach (TRISTAN project) Raphael Kunz (Infineon Technologies, DE) Bio: Raphael Kunz received his B.S. degree in Software Engineering in 2020 and his M.S. degree in Software Engineering with a specialization in Embedded and Distributed Systems in 2024 from the University of Ulm, Germany. During his studies, he worked in research and development for Mercedes-Benz and Continental. He is currently a doctoral student at the Chair of Electronic Design Automation at the Technical University of Munich and Infineon Technologies AG in Germany. His research focuses on software generation and generation of runtime systems. Abstract: The increasing importance of languages like Rust in embedded programming, alongside traditional C, highlights the need for adaptable coding styles. Embedded systems require flexibility in coding approaches due to varying language constructs, run-time systems, CPU architectures, and hardware peripherals. This talk introduces an extension to the existing model-based code generator aligned with the Model-Driven-Architecture (MDA) to generate code in Rust alongside the existing C-setup. This talk highlights the generation of different target-specific implementations of software in both Rust and C while only maintaining one model. The generated software can differ in the provided and handled data types as well as the method of processing the data depending on the selection. Therefore, increasing the reusability of written software. In this presentation, we want to highlight our progress in implementing the Rust generation and the achieved results.

12:55 - 13:55
Lunch

13:55 - 17:00
Session: Virtual Prototyping and Verification
Moderator: Daniel Müller-Gritschneder (TU Wien, AT)

13:55	Software Performance Simulation with ETISS: Status and Ongoing Work (GenerIoT project) Conrad Foik (Technical University of Munich, DE) Bio: Conrad Foik received his master‘s degree in electronics from the Norwegian University of Science and Technology (NTNU) in 2015. After working as an R&D engineer in the industry, he is currently a PhD candidate at the Chair of Electronic Design Automation at the Technical University of Munich (TUM). His research interests are design methods at the Electronic System Level (ESL) with a focus on performance estimation. Abstract: We present our software performance simulation environment based on ETISS instruction set simulator. Our approach is flexible, enabling quick adaptation to new microarchitecture variants, and capable of delivering highly accurate performance estimates and high simulation speeds. We also outline our on-going work focusing on modelling branch prediction schemes and memory systems. Slides (Access for event attendees only)
14:25	Using DBT-RISE based VP for Early performance estimation of software using custom instructions (Scale4Edge and TRISTAN projects) Eyck-Alexander Jentzsch (MINRES Technologies, DE) Bio: Eyck-Alexander holds a B.Sc. in Physics from the TU Munich. He has been a software developer at Minres Technologies GmbH for 3 years and currently works mainly on VP and firmware. Abstract: In modern software development, early performance estimation is crucial for optimizing applications, particularly when integrating custom instructions into RISC-V-based systems. This presentation explores the use of DBT-RISE, a dynamic binary translation library for Instruction Set Simulators (ISS), to achieve accurate performance predictions during the early stages of hardware and software co-development. By leveraging DBT-RISE as a virtual platform (VP), we demonstrate how to efficiently simulate and evaluate the impact of custom instructions on system performance. This approach is particularly relevant for RISC-V firmware development, providing developers with critical insights to guide optimization and decision-making before hardware availability. Slides (Access for event attendees only)
14:55	Break: Coffee/Tea Break
15:25	From Simulation to RVV Hardware: Evaluating the muRISCV-NN TinyML Inference Library on the CanMV K230 Platform (Scale4Edge project) Benedikt Witteler (Technical University of Munich, DE) Philipp van Kempen (Technical University of Munich, DE) Bio: Philipp van Kempen is working in the Electronic System Level (ESL) group of the EDA chair developing compiler solutions for deployment challenges related to Extreme Edge AI applications (TinyML), mainly for RISC-V targets. This includes optimizations at several stages of the design process (Training, Hardware Design and SW/ML Deployment) e.g. by using Network Architecture Search (NAS), improving existing machine learning tools and proposing ISA extensions in a highly automated fashion. Abstract: The ratification of the RISC-V Vector Extension (RVV) is bringing new momentum to the RISC-V ISA in the field of embedded machine learning. muRISCV-NN is a library of efficient deep learning kernels that leverages RVV for inference on constrained edge devices. With the CanMV K230 development board - the first commercial hardware implementing RVV 1.0 - this study evaluates whether muRISCV-NN can perform as effectively on real hardware as in an instruction set simulator (ISS). Porting muRISCV-NN to the CanMV K230 involved addressing challenges like compiler issues and its integration within RTOS and Linux environments. The results of this project show that muRISCV-NN meets its performance expectations, achieving a 3.85x cycle count reduction during ResNet inference through vectorization. Layer-wise benchmarking with the MLonMCU framework revealed speedups of up to 6.68x in fully connected layers and up to 4.40x in Conv2D layers, with larger layers profiting more from vectorization than smaller ones. These findings confirm muRISCV-NN’s effectiveness on physical hardware, supporting the broader adoption of RISC-V in embedded AI. Slides (Access for event attendees only)
15:55	Fast RISC-V Firmware Validation with QEMU (ISOLDE project) Frederik Haxel (FZI, DE) Bio: Frederik Haxel studied computer science (B.Sc.) and electrical engineering (B.Sc. & M.Sc.) at the Karlsruhe Institute of Technology (KIT). Since 2017 he is a research assistant at the FZI Research Center for Information Technology. His research interests include safety-critical systems, HW/SW co-design and RISC-V. Abstract: QEMU is a well-established tool for fast system emulation, with extensive RISC-V support, and a wide range of peripheral simulation models. However, using QEMU to develop firmware for a specific board is often impractical due to the very small number of actual platforms supported by QEMU and the high probability that at least some peripherals are not included in the QEMU simulation models. In this presentation, we will demonstrate our work based on the Xilinx fork of QEMU, which aims to simplify and accelerate the firmware development and validation with QEMU. Instead of selecting a pre-existing RISC-V platform, the platform is dynamically generated from a device tree description. Peripherals without an existing simulation model can be replaced with a generated RTL co-simulation model. This not only enables the execution of the actual firmware binary in QEMU, but also provides a foundation for further hardware simulation approaches. Slides (Access for event attendees only)
16:25	Wrap-Up of Day 1 Timo Hämäläinen (Tampere University, FI) Daniel Müller-Gritschneder (TU Wien, AT)

19:00 - 22:00
Social Event

Friday, October 25, 2024

09:00 - 09:10
Welcome

09:10 - 12:10
Session: Firmware Coding and Code Generation
Moderator: Sebastian Prebeck (Infineon Technologies AG)

09:10	Enhancing RISC-V Code Generation with Automated Intrinsic Handling for Custom ISAs (MANNHEIM-FlexKI and TRISTAN projects) Mayuri Bhadra (Infineon Technologies, DE) Bio: Mayuri Bhadra received her B.E. degree in Electronics and Telecommunication Engineering in 2018 from Mumbai University, India, and her M.S. degree in Information Technology with a specialization in Embedded Systems in 2021 from the University of Stuttgart, Germany. From 2021 to 2023, she worked as an ASIC Verification engineer at Bosch GmbH. She is currently a doctoral student at the Chair of Electronic Design Automation at the Technical University of Munich and Infineon Technologies AG in Germany. Her research focuses on hardware/software codesign and deriving optimized neural network (NN) kernel libraries from accurate machine descriptions of ML accelerators. Abstract: RISC-V's open ISA enables custom instructions while maintaining standard compatibility. This flexibility has led to diverse RISC-V core implementations, each optimized for specific applications and algorithms. This talk explores key drivers and challenges in intrinsic design and presents a structured approach to generating portable code with intrinsic notations using formal models. The talk can be further summarized as follows: • Custom CPU instructions for low-level tasks and compute-intensive applications • Efficiently supporting various intrinsic across different CPU cores and variants • Automated intrinsic handling approach integrating with existing code generation flow • Generating kernel libraries for tensor math operators on commercial RISC-V variants, including RVI, RVP, and custom instruction extensions
09:40	Firmware design for microcontrollers with the open source event-driven operating system (ISOLDE project) Samuel Ardaya-Lieb (Consolinno Energy, DE) Abstract: The development of bare-metal firmware for microcontrollers requires not only an understanding of a hardware-oriented programming language such as C or C++, but also solutions for real-time capability and software architecture. The open source event-driven operating system (OpenEDOS) addresses these challenges by providing a firmware core, which is written in C and implements a scalable, efficient, event-driven architecture using an event loop as the main routine of a context. Within an event loop, software modules communicate via a message-based request-response protocol that allows for cooperative multitasking. If required for real-time capability, several event loops can be distributed to threads (e.g. tasks of an RTOS). In addition to the core, OpenEDOS offers the system builder, a command line interface (CLI) that can automatically generate source code from given API definitions. In the workshop, the technical functionality of the system and an example use case from the ISOLDE project will be presented. Slides (Access for event attendees only)
10:25	Break: Coffee/Tea Break
10:55	Compute-accelerator driver APIs: Supporting efficient code-generation by compilers as well as direct use by application programmers (MANNHEIM-FlexKI project) Andrew Stevens (Infineon Technologies, DE) Bio: Andrew Stevens is Lead Principal Engineer for embedded AI/ML deployment tooling at Infineon Technologies AG. Andrew graduated in Computer Science from the University of Warwick, gaining his Ph.D in Artificial Intelligence from the University of Edinburgh in 1986. After post-doctoral research into automated theorem proving systems for hardware/software verification at Oxford University he joined Philips Semiconductors intending to work as a compiler/code-generation specialist. It turned out compilers weren’t needed but instead there was a great deal of extremely rewarding systems-design and modelling work. This led to Andrew taking the lead concept (and emergency real-time firmware) engineering roles for the SAA6745 LCD-TV IC. Restructuring at Philips led to an intense but enjoyable spell working at a Behavioural Synthesis (hardware compiler) startup (ChipVision gmbh) before finally joining Infineon Technologies in 2009. In 2019, after successfully leading the development of Infineon’s in-house systems modelling tool suite “Inicio”, he took on the role of technical lead in a newly formed AI/ML team in the companies design engineering support group. His currently activities within Infineon technologies focus on toolchain support for machine learning in resource-constrained embedded systems. His greatest regret is sensibly concentrating on finishing a deadly-dull theorem-proving PhD rather than abusing the workstations left in his care to play around with early neural networks. Abstract: To provide a stable abstract programming interface for non-processor compute accelerators vendors typically provide layered application programming interface (API) libraries ("driver stacks") similar to those used for I/O peripherals. These APIs are effective for human-written application code and as targets for code-generation by high-level compilers. However, relying on such APIs impacts efficiency: compilers cannot optimize below or across the API entry-points. The resulting inefficiencies are commercially significant for hard real-time sense/control applications on high-volume/low-cost embedded platforms. We illustrate the inefficiencies introduced by targeting API stacks using code-samples and benchmarks from recent Infineon products. Comparing these with "ideal" compiler outputs, we propose a modified driver stack architecture. This supports programming of compiler backends; allowing efficient code to be generated without significantly increasing API development effort or compromising direct use in human-programmed application code.
11:25	Non-intrusive and continuous monitoring and analysis of program execution (TRISTAN project) Alexander Weiss (Accemic Technologies, DE) Bio: Alexander studied electrical engineering at the Technical University of Munich and received his doctoral degree in computer science from the Technical University of Dresden. He holds several patents, is the author of a number of papers in internationally recognized journals (e.g. IEEE Computer), and has outstanding expertise in the areas of safety-critical systems, embedded software test methods, and hardware and FPGA development. Alexander is founder of Accemic Technologies, a Munich area based company specializing in non-intrusive and continuous monitoring of embedded processors. Abstract: This presentation introduces a trace IP for RISC-V, enabling non-intrusive monitoring of program execution, even for firmware. The trace IP is part of a comprehensive toolchain, which includes a compiler, an external trace tool, and analysis utilities, and is designed around detailed use cases such as test impact analysis, WCET estimation, and performance optimization. The talk outlines the requirements for monitoring both module and integration tests and demonstrates how the toolchain effectively analyzes non-instrumented release code. Slides (Access for event attendees only)
11:55	Wrap-Up of Day 2 Wolfgang Ecker (Infineon Technologies, D)

12:10 - 13:10
Lunch