FEST: Functional Verification of Systems

The semiconductor and chip industry are forming a market where functional requirements, complexity, time to market, cost pressure and shorting-living products are increasing dramatically. To compete in this market, a qualified verification process with short turnaround times is a key figure especially in markets with strong requirements regarding security and reliability of SoCs. The miniaturization of SoCs comes along – beside several advantages – with new challenges and questions in the design process that lead to technical and economic risks.

The aim of the FEST project is to research solutions for the unifi-cation of the SoC verification process by closing verification gaps from system level down to electric level. In this project, promising solutions are clustered to vision a coherent verification process. By using these new verification methodologies in future, the risks of re-design can be reduced, the time to market can be shortened or even a protection of market share can be achieved. Additionally, SoCs with more complexity then can be verified by formal methods.

Classification in the edaMatrix:

Used Abbreviations