VeronA: Verification of Analog Circuits

The VeronA project creates a basis for an automated verification of analog circuits and systems. Its goal is to develop fundamental elements of an integrated verification methodology for integrated analog circuits, such that the analog parts of mixed-signal chips can be verified along with the digital part. Therefore, new methods and tools are developed which exploit formalized verification and target verification-oriented modeling. The following technical goals are in the focus of the project:

• Development of methods and rules for the creation of models which are suitable for verification in different levels of abstraction, because they can be simulated quickly and also sufficiently describe many physical effects (e.g. mixed-discipline or temperature).
• Investigation and development of formal verification methods for analog circuits, namely model checking and equivalence checking.
• Development of methods for assertion-based verification, as well as of formal procedures for performance and tolerance verification.
• Implementation of an integrated methodology for multilevel verification of analog systems considering mixed-signal/mixed-domain aspects and using the aforementioned points

Thereby, emphasis is laid on the suitability of the developed methods for industrial application. The project results will essentially improve efficiency and quality of verification, which will ultimately lead to qualitatively higher valued and more reliable electronic products.

Classification in the edaMatrix:

Used Abbreviations