Physical Verification Flow for Hierarchical Analog IC Design Constraints

Authors: Volker Meyer zu Bexten, Infineon Technologies A...; Markus Tristl, Infineon Technologies AG, DE; Göran Jerke, Robert Bosch GmbH, DE; ; Dina Medhat, Mentor Graphics (Egypt)

Zusammenfassung:

Konferenz

2015 20th Asia and South Pacific Design Automation Conference (ASP-DAC)

Seiten 447 - 453

Publication Date: 2015/01/20

Location of Publication: 20th Asia and South Pacific Design Automation Conference (ASP-DAC), Chiba/Tokyo, Japan

Keyword: Automotive