Authors: Christoph Kuznik, Universität Paderborn, DE; Wolfgang Mueller, Universität Paderborn, DE; Gilles Bertrand Defo, Universität Paderborn, DE
Abstract:
The ever-increasing complexity of heterogeneous electronic systems demand for intensified abstraction and automation efforts to improve design, verification and validation productivity, especially in earlier phases of system engineering. Within the verification activity various metrics can be applied to determine functional correctness or the overall progress. Here, a supporting verification methodology defining high-level verification planning down to the actual metric code development is essential. Moreover, an advanced assistance for the designer, such as a tooling infrastructure to automatize and accelerate the metric code implementation, is needed to minimize the influence of errorprone manual coding. In this article we present a single-source verification metric code-generation methodology for improved coverage automation. We determine (i) a suitable metric model for model-based capture of verification metrics as well as (ii) an assisted model-based processing and generation flow of the verification environment and metric skeletons. We apply our method to a SystemC case-study, in doing so, targeting metric code implementation productivity and consistency enhancement.
Publication Date: 2014/06/01
Location of Publication: Electronic System Level Synthesis Conference (ESLSyn) 2014, San Francisco, CA, US
Keywords: System Design; Verification
