Authors: Andreas Mauderer, Robert Bosch GmbH, DE; Jan-Hendrik Oetjens, Robert Bosch GmbH, DE; Venkateshwar Krishnamurthy, Robert Bosch GmbH, DE; Thomas Schumann, Hochschule Darmstadt, Elektro- und Informationstechnik, DE
Abstract:
Due to the increasing complexity of System-on-Chip (SoC) designs and shorter time-to-market, Virtual Prototyping has become an established approach for an early validation of system concepts and and early software development. Moreover, IP-XACT has established itself as a standard for describing memory maps and architectures. Synopsys TLM Creator already allows generating SystemC module wrappers based on IP-XACT register descriptions. In order to further accelerate the construction of Virtual Prototypes and to ensure consistency between Virtual Prototypes and RTL implementations, this paper presents an approach for the automated construction and configuration of Synopsys Virtualizer architectures based on IP-XACT architecture descriptions. The developed automated code generator is implemented using Java Emitter Templates (JET) and is integrated in our IP-XACT-centric EDA design flow. Furthermore, possibilities for describing TLM architectures in IP-XACT will be discussed and a developed approach for this description will be presented. Finally, the presented code generation approach will be applied by taking the example of a complex SoC design.
Publication Date: 2015/06/25
Location of Publication: SNUG Germany 2015, München, DE
Keywords: Automotive; System Design
