Authors: Markus Becker, Universität Paderborn, DE; Christoph Kuznik, Universität Paderborn, DE; Wolfgang Müller, Universität Paderborn, DE; ; Bastian Koppelmann, Universität Paderborn, DE; Bernd Messidat, Universität Paderborn, DE
Abstract:
In this paper, we present an efficient approach to virtual platform modeling for TriCore-based SoCs by combining fast and open software emulation with IEEE-1666 Standard SystemC simulation. For evaluation we consider Infineon's recently introduced AURIX processor family as a target platform, which utilizes multiple CPU cores operating in lockstep mode, memories, hierarchical buses, and a rich set of peripherals. For SoC prototyping, we integrate the fast and open instruction accurate QEMU software emulator with the TLMu library for SystemC co-verification. This article reports our most recent efforts of the implementation of the TriCore instruction set for QEMU. The experimental results demonstrate the functional correctness and performance of our TriCore implementation.
http://dvcon-europe.org/conference/dvcon-europe-2014/
Publication Date: 2014/10/14
Location of Publication: Design and Verification Conference (DVCON EUROPE), Munich, Germany
Keywords: System Design; Verification
