Design Cost Modeling and Data Collection Infrastructure
Business Session 1
Measure or Die - Design Productivity
Andrew B. Kahng, Professor at the Computer Science Department University of California, San Diego
Abstract
The 2001 International Technology Roadmap for Semiconductors introduced a new design cost model that highlighted both the cost of design and the benefits of EDA technology. For practical evaluation and optimization of design cost, standard measurement infrastructure is needed.
This talk reviews experience with METRICS, an open-source infrastructure developed in the MARCO Gigascale Systems Research Center. METRICS allows instrumentation of design tools and design processes, collection of design artifact and design process data, and prediction of future results and data based on current information. The end goal is a "science, rather than an art" of chip design and implementation - and the key precept is that design processes must be measured before they can be improved. METRICS (1) unobtrusively gathers characteristics of design artifacts, design processes, and communications during the system development effort, and (2) analyzes and compares that data to analogous data from prior efforts.
A variety of benefits can result, including resource prediction, go / no-go decision support, project monitoring, design flow debugging and error prevention, benchmarking, and identification of good predictors and new metrics that reflect eventual design success. Example applications in a chip implementation flow will be reviewed.
Curriculum Vitae
Andrew B. Kahng is a professor in the UC San Diego CSE and ECE departments. He was the founding General Chair of the International Symposium on Physical Design and will co-chair the Design Automation Conference program committee in 2004. He has also been active in the MARCO Design and Test Focus Center, where his theme has built infrastructures for roadmapping, open-source CAD IP, and metrics collection for design process optimization. His research centers on physical design and performance analysis of VLSI, as well as the VLSI design-manufacturing interface.
