1st International Workshop on RISC-V Research Activities - Program
At this web page you find the programme of the 1st International Workshop on RISC-V Research Activities. You may expand the programme for each session by clicking on the session title. You will find the detailed timetable, presentation titles and author names. If additional information like an abstract, curriculum vitae or (for attendees of the 1st International Workshop on RISC-V Research Activities only) slides is available, a link below the presentation title is displayed.
Thursday, June 21, 2018
09:00 - 09:30
Session 0: Welcome & Introduction
09:30 - 12:00
Session 1: RISC-V Virtual Platforms
| 09:30 | Extendable Translating Instruction Set Simulator (ETISS) with RISC-V Support and SYstemC/TLM Pulpino Virtual Platform |
| 09:45 | Extensible and Configurable RISC-V based Virtual Prototype |
| 10:00 | MINRES Assets & Interests project ideas in the area of VP based design and development methods |
| 10:15 | Discussion |
| 10:30 | Break: Coffee Break |
| 10:45 | Current and Future Activities for RISC-V Virtual Prototyping and Chip Design |
| 11:00 | A context-sensitive PEG-based timing model for a PULPINO-derived RISC-V microprocessor |
| 11:15 | Discussion |
12:00 - 13:00
Lunch Break
13:00 - 15:30
Session 2: RISC-V-Hardware-Architecture and Extensions
| 13:00 | Design of an Ultra Low Power RISC-V Platform with On-Chip-Tracing in 22FDX |
| 13:15 | Hardware/Software Co-Design with the Rocket-Chip Generator |
| 13:30 | A Low-Latency Lean DDR3 Controller and PHY in 65nm for PULP(ino) based Systems |
| 13:45 | Discussion |
| 14:00 | Break: Coffee Break |
| 14:15 | Analyzing OpenSource for Safety and Security Applications |
| 14:30 | Automated Verification of RISC-V-conform Floating-Point Modules |
| 14:45 | Discussion |
14:00 - 14:15
Coffee Break
15:45 - 17:15
Session 3: Future Research
| 15:45 | Identification and discussion of research topics |
| 16:45 | Wrap up |
