Reducing Verification Risk to Increase overall prifitability
![Printer-friendly version Printer-friendly version](/sites/all/modules/print/icons/print_icon.gif)
![Send by email Send by email](/sites/all/modules/print/icons/mail_icon.gif)
![PDF version PDF version](/sites/all/modules/print/icons/pdf_icon.gif)
edaForum05 Presentation
Company Presentation
Cadence Design Systems, Inc. "Reducing Verification Risk to Increase overall profitability"
Abstract
In today s competitive electronics industry the ability to reduce risk can have a huge impact on the overall profitability of the product and the company bottom-line. Verification is all about eliminating risks in the design process to ensure that the product meets specifications, ships without bugs, and ships on time. The complexities of verification, however, are driving project teams to consider adding considerable risks to their current processes, all in order to reduce risks! This is a fundamental paradox facing every project team today. How can you add risks to reduce risks? New languages, new methodologies, and new technologies each can introduce significant risks to the design process. If they are coupled properly, however, and the right solution is chosen for the right application and engineering specialist or team of specialists, then risks can significantly be reduced. This presentation will focus on reducing risk in three areas:
1. productivity risks - project get more complex, and verification grows in an exponential relationship to the design, and often productivity take a nose dive,
2. quality risks - many teams employ few metrics and don t have a comprehensive verification plan that is linked to their specification that they measure against, and therefore, most don t focus on verifying everything they need to verify, and they also don t deploy the proper technology and methodology combinations to catch bugs at the IP or Unit level, which has to be verified in a chip and system context, and
3. predictability risks - the combination of productivity risks and quality risks leads to an ever growing lack of predictability to the verification process, which leads to multi-month slips on a good project.
This presentation will provide insight into how the new Cadence Verification Division offerings (post Verisity merger) is evolving into a cohesive set of solutions to address executives who require better visibility into the design process so that they can reduce risk and increase profitability.