Cadence Design Systems, Inc: "Unified Verification Methodology" and "Custom IC Platform"

Company Presentation: Cadence Design Systems, Inc.

Abstract

Functionally verifying nanometer-scale ICs requires optimal speed and efficiency. Yet today’s fragmented methodologies make it impossible to optimize either. Each verification stage has its own methodology, environment, tools, languages, models, user interface, and APIs. Engineers must re-create almost everything at every stage. The result is a slow, grossly inefficient, expensive process that often allows critical bugs to reach silicon. “Smart” verification techniques that apply to only a single verification stage cannot even begin to address fragmentation. Successful IC design teams need to adopt a unified verification methodology.

"Custom IC Platform - From System Specification to Silicon Implementation"

Cadence has always viewed Custom IC design as something more than a bunch of point tools. For successful design, there must be a smooth and cohesive flow between the Invention and the Implementation phase of the design. A complete design platform with a high level of automation enabling a seamless top-down design for integrated analog and mixed-signal systems will be presented.

Over the last 6 months, we have taken specific steps to increase the interoperability of the Custom IC tools, both within our own flow and neighboring flows. One of the changes we have made is to identify a method for capturing your design specifications in a central location and be able to always check your design against the specification. Besides this we have also brought in new technology to create a "Silicon Calibrated Library" so that you can start from accurate silicon data and end with first silicon correct. Finally OpenAccess our new common database is designed to allow free IP exchange not only within Cadence but also throughout the industry.