Authors: Saed Abughannam, Universität Paderborn, DE; Wolfgang Müller, Universität Paderborn, DE; ; Wolfgang Ecker, Infineon Technologies AG, DE; Cristiano Novello, Infineon Technologies AG, DE; L. Wan, Universität Paderborn, DE
Zusammenfassung:
The design of safety critical systems requires an efficient methodology for an effective fault effect simulation for analog and digital circuits where analog fault injection and fault effect simulation is currently a field of active research and commercial tools are not available yet. This article begins by discussing fault injection strategies for analog circuits applied on a case study with two topologies of a Voltage Controlled Oscillator (VCO). In the second part it performs on the basis of the example of a Wireless Sensor Network (WSN) node, how far different mixed level implementations with Verilog-A and SPICE can affect the simulation time and points out which component consumes the major part of the simulation time.
Publication Date: 2016/09/12
Location of Publication: Analog 2016, Bremen, DE, 12.09.2016
Keyword: Verification
